A. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
B. Description of the Related Art
A discrete semiconductor with a high breakdown voltage plays an important role in a power conversion device. For example, an insulated gate bipolar transistor (IGBT) or an insulated gate field effect transistor (MOSFET) has been known as a discrete semiconductor. In particular, since the IGBT has the property that an on voltage is reduced by conductivity modulation, it is applied to a case in which power conversion is required at a high voltage.
In recent years, a reverse blocking IGBT (RB-IGBT) has been developed which has a termination structure in which a high breakdown voltage (hereinafter, referred to as a reverse breakdown voltage) is obtained when a reverse bias is applied to a pn junction including a collector region and a drift region of the IGBT. For example, the reverse blocking IGBT has started to be applied to an AC (alternating current)/AC direct conversion device.
FIG. 26 is a cross-sectional view illustrating the reverse blocking IGBT according to the related art. The reverse blocking IGBT illustrated in FIG. 26 includes active region 100 in which an element structure of an IGBT is formed in n− wafer 101 which will be an n− drift region and breakdown voltage structure 110 which surrounds active region 100. In active region 100, for example, a surface element structure of a planar-gate-type IGBT including a p base region or an n+ emitter region, a gate electrode, and an emitter electrode is formed in the first main surface of wafer 101. P collector region 102 is provided on the entire second main surface of wafer 101. Collector electrode 103 comes into contact with p collector region 102.
In breakdown voltage structure 110, a plurality of p-type regions 111 and a plurality of conductive films 112 which come into contact with p-type regions 111 are provided in the first main surface of wafer 101. A p-type isolation region (hereinafter, referred to as a through silicon isolation region) 121 is provided at outer circumferential end 120 of wafer 101 such that it extends from the first main surface of wafer 101 to the drift region and comes into contact with p collector region 102. Isolation region 121 surrounds breakdown voltage structure 110. Breakdown voltage structure 110 and outer circumferential end 120 (termination structure) surround active region 100.
For example, isolation region 121 of the reverse blocking IGBT is formed as follows. First, p-type impurities are implanted from the first main surface of wafer 101. Then, a heat treatment is performed for a long time to diffuse the implanted p-type impurities deep into the second main surface of wafer 101. In this way, isolation region 121 obtained by diffusing the p-type impurities is formed. Then, wafer 101 is ground from the second main surface of wafer 101 such that isolation region 121 is exposed. In this way, isolation region 121 which extends from the first main surface to the second main surface of wafer 101 is formed.
As a method of forming the isolation region of the reverse blocking IGBT, the following method has been proposed. An n− silicon substrate has a bottom and an upper surface which are opposite to each other. A p-type impurity diffusion layer is formed at a high concentration on the entire bottom of the n− silicon substrate by the diffusion of the p-type impurities. In addition, a p-type isolation region is partially formed in the upper surface of the n− silicon substrate by the diffusion of the p-type impurities. The p-type isolation region has a bottom which reaches the upper surface of the p-type impurity diffusion layer (for example, see JP 2004-165619 A).
FIG. 27 is a cross-sectional view illustrating another example of the reverse blocking IGBT according to the related art. In the reverse blocking IGBT illustrated in FIG. 27, p-type isolation region 130 is provided along the side wall of a trench which extends from the first main surface of wafer 101 to p collector region 102 and is connected to p collector region 102. The trench surrounds active region 100 and breakdown voltage structure 110 of wafer 101. The trench is filled with filler 131.
As a method of forming the isolation region with the trench structure, the following method has been proposed in which a step of forming a first impurity region of a second conduction type in a second main surface of a semiconductor substrate which is a first conduction type and has a first main surface and the second main surface opposite to the first main surface, a step of forming a trench which extends from the first main surface to the first impurity region in a peripheral region of the semiconductor substrate using anisotropic etching, and a step of introducing second-conduction-type impurities from the side wall of the trench to the semiconductor substrate using ion implantation to form a second impurity region are sequentially performed (for example, see JP 2005-093972 A).
FIG. 28 is a cross-sectional view illustrating another example of the reverse blocking IGBT according to the related art. In the reverse blocking IGBT illustrated in FIG. 28, active region 100 and breakdown voltage structure 110 are provided in wafer 101. Isolation region 122 is provided in a first main surface of outer circumferential end 120 of wafer 101. In addition, concave portion 123 which extends from a second main surface to the first main surface through isolation region 122 is provided at outer circumferential end 120 of wafer 101.
The angle between the side wall of concave portion 123 and the second main surface of wafer 101 is, for example, 54.7°. That is, outer circumferential end 120 of wafer 101 is thinner than active region 100. P collector region 102 and p-type region 124 are provided in the second main surface of wafer 101 and the side wall of concave portion 123. Isolation region 122 is connected to p collector region 102 through p-type region 124.
For example, the reverse blocking IGBT illustrated in FIG. 28 is manufactured as follows. First, the first main surface of wafer 101 is a (100) plane and isolation region 122, the surface element structure of the reverse blocking IGBT, and the breakdown voltage structure are formed on the first main surface of wafer 101. Then, wafer 101 is thinned to a predetermined thickness from the second main surface of wafer 101.
Then, concave portion 123 which extends from the second main surface of wafer 101 to isolation region 122 is formed by photolithography. For example, concave portion 123 is formed by wet etching such that the angle between the side wall of concave portion 123 and the second main surface of wafer 101 is, for example, 54.7°. Then, a resist mask for forming concave portion 123 is removed. Then, ion implantation and laser annealing are performed to form p collector region 102 and p-type region 124 in the second main surface of wafer 101 and the side wall of concave portion 123.
As a method of forming the isolation region in the semiconductor wafer in which the outer circumferential end is thinner than the active region, the following method has been proposed. The surface of a thin semiconductor wafer in which a surface structure forming a semiconductor chip is formed is attached to a supporting substrate by a double-sided adhesive tape. Then, a trench to be a scribe line is formed from the rear surface of the thin semiconductor wafer by wet anisotropic etching, with the crystal plane thereof being exposed. Then, an isolation layer which maintains a reverse breakdown voltage is formed on the side of the trench whose crystal plane is exposed by ion implantation and low-temperature annealing or laser annealing at the same time as a p collector region, which is a rear diffusion layer, is formed (for example, see JP 2006-303410 A and Kazuo Shimoyama and five others, “A New Isolation Technique for Reverse Blocking IGBT with Ion Implantation and Laser Annealing to Tapered Chip Edge Sidewalls),” (Italy) ISPSD' 06: Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's 2006), June 4-8, 2006, pp. 29-32).
As a method of forming the collector region of the IGBT, a method has been proposed which forms the collector region using SDB (Silicon Direct Bonding) which directly bonds two wafers (for example, see Akio Nakagawa and four others, “1800V Bipolar-Mode MOSFETs: A First Application Wafer Direct Bonding (SDB) Technique to Power Device,” (US), IEDM: 1986 International Electron Devices Meeting), 1986, Vol. 32, pp. 122-125).
FIGS. 29 to 31 are cross-sectional views illustrating an IGBT manufacturing process according to the related art. The method of forming the collector region of the IGBT using SDB will be described with reference to FIGS. 29 to 31. First, a first n− wafer 201 and a second p+ wafer 204 are prepared and the surfaces thereof are mirror-polished. Then, as illustrated in FIG. 29, for example, phosphorous (P) ions are implanted and a thermal activation process is performed to form n+ region 202 with a resistivity lower than that of first wafer 201 on the first main surface of first wafer 201. Then, as illustrated in FIG. 30, for example, boron (B) ions are implanted and a thermal activation process is performed to form p+ region 203 on a surface layer of n+ region 202.
Then, as illustrated in FIG. 31, the main surface of first wafer 201 close to p+ region 203 and the first main surface of second wafer 204 are hydrophilized and directly bonded to each other at room temperature. That is, interface 200 between the bonded wafers is a boundary surface between p+ region 203 and second wafer 204. Then, annealing is performed on a wafer obtained by bonding first wafer 201 and second wafer 204 at a temperature of 1000° C. or more in a nitrogen atmosphere to increase the bonding strength between the wafers. Then, the second main surface of first wafer 201 is ground and thinned to a desired thickness. In this way, a collector region including p+ region 203 and second wafer 204 is formed in the wafer obtained by bonding first wafer 201 and second wafer 204.
As another method, the following method has been proposed. In the method illustrated in FIGS. 29 to 31, p+ region 203 is not formed in the first main surface of first wafer 201 and the surface of n+ region 202 of first wafer 201 and the first main surface of second wafer 204 are bonded to each other. That is, the interface between the bonded wafers is a boundary surface between n+ region 202 and second wafer 204. Then, a method has been proposed in which first wafer 201 is thinned from the second main surface to form a collector region including only second p+ wafer 204 (for example, see U.S. Pat. No. 5,541,122). U.S. Pat. No. 5,541,122 discloses the formation conditions of n+ region 202. The method illustrated in FIGS. 29 to 31 discloses the formation conditions of n+ region 202 and p+ region 203.
As another method, the following method has been proposed. FIG. 32 is a cross-sectional view illustrating a semiconductor device formed by bonding wafers according to the related art. A method has been proposed in which surface structures 212 and 213 of the semiconductor device are formed on the first main surface and the second main surfaces of two wafers 211 and 214 which are thinned from the second main surface are directly bonded to each other to form a semiconductor device. That is, interface 210 between the bonded wafers is a boundary surface between first wafer 211 and second wafer 214 (for example, see U.S. Pat. No. 6,194,290).
As a general method for bonding the wafers, the following methods have been proposed: a method of integrating wafers through H2O absorbed to “Si—OH—” in the surfaces of the wafers; a method of replacing “—F” with high surface density which is attached to the surface of the wafer with “—OH” and bonding the wafer to a wafer having an insulating layer formed therein; and a method of providing an n+ semiconductor layer with a resistivity lower than that of an n− semiconductor layer between an insulating layer and the n− semiconductor layer serving as an active layer on an SOI substrate to obtain a gettering effect for metal contamination (for example, see JP 4232645 B1).
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.